In general, as a low voltage is gradually applied for an operation of a semiconductor memory device, an operation voltage margin for a threshold voltage of an NMOS transistor or a PMOS transistor becomes insufficient. As a result, an operation feature of a sensor amplifier deteriorates.
The sense amplifier includes an NMOS transistor for a pull-down operation and a PMOS transistor for a pull-up operation. There are significant changes in an average value of threshold values of the NMOS transistor and the PMOS transistor constituting the sense amplifier. The different between PMOS transistors for the pull-up operation is greater than that of NMOS transistors for the pull-down operation. Therefore, an offset voltage of a PMOS amplifier is significantly larger than that of an NMOS amplifier.
In the case of a low voltage operation, driving capability of an amplifier deteriorates. For this reason, the aforementioned phenomenon takes an important role in the determination of an operation feature.
Referring to FIGS. 1a and 1b, the X-axis of FIG. 1b is associated with threshold voltages of a right NMOS transistor and a right PMOS transistor shown in FIG. 1a. Further, the Y-axis of FIG. 1b is associated with threshold voltage of a left NMOS transistor and a left PMOS transistor shown in FIG. 1a. To obtained the view of FIG. 1b, the threshold voltages of the respective NMOS transistors and PMOS transistors included in a plurality of sense amplifiers are measured and are respectively mapped into the coordinates.
Referring to the figures, in the case of NMOS transistors, the threshold voltage features of the left NMOS transistor and the right NMOS transistor are uniformly distributed. On the other hand, in the case of PMOS transistors, the threshold voltage features the left PMOS transistor and the right PMOS transistor are dispersed, thereby showing non-uniform distribution.
A conventional sense amplifier S/A is provided for a cell array as shown in FIG. 2. FIG. 2 illustrates an example of a folded bit line structure.
A cell is composed of one NMOS transistor controlled by a word line WLn and one capacitor. The drain of the NMOS transistor is connected to a bit line. The source of the NMOS transistor is connected to one electrode of the capacitor, wherein its connection point is defined as a storage node SN at which writing charges are stored. The other electrode of the capacitor is a plate electrode PL. The plate electrode PL is connected to a common cell plate and is supplied with a cell plate voltage. The cell plate voltage is generally VDD/2, where VDD is defined as a high operation voltage of the cell.
Bit lines BL and /BL are connected to the sense amplifier S/A. When the word line WL0 is activated and thus cell data is delivered to the bit line BL, the bit line /BL provides a reference voltage. On the contrary, when the word line WL1 is activated and thus the cell data is delivered to the bit line /BL, the bit line BL provides the reference voltage. In a data buffer and the sense amplifier S/A, data is input and output through local data buses LDB and LDBB.
FIG. 3 is a circuit diagram of a latch type sense amplifier.
A pull-up activation stage of the latch type sense amplifier is controlled in response to a control signal SAP. A pull-down activation stage of the latch type sense amplifier is controlled in response to a control signal SAN.
For a pre-charge operation, a bit line pre-charge voltage VBLP is supplied to the bit lines BL and /BL by using an equalizing signal BLEQ. Here, the bit line pre-charge voltage VBLP may be defined as VDD/2.
A column selection signal YI is used to select the sense amplifier in order to exchange data between bit lines BL and /BL and local data buses LDB and LDBB. Bit line selection signals BISH and BISL are used to exchange data through the bit lines BL and /BL between the sense amplifier and the cell array.
An equalizing signal BLEQ is used to equalize a voltage between the bit lines BL and /BL.
The circuits of FIGS. 2 and 3 operate in the same manner as a circuit of FIG. 4. Specifically, in a pre-charge period, the bit lines BL and /BL and the control signals SAN and SAP are pre-charged to the bit line pre-charge voltage VBLP.
In a charge share period that comes after the pre-charge period, the word line WL is activated, and as a result, cell data is loaded on the bit line BL.
Thereafter, in a sense amplify period, to amplify signals of the bit lines BL and /BL, the control signal SAN transits to a ground voltage, and the control signal SAP transits to the voltage VDD. Therefore, the bit lines BL and /BL are amplified to a cell high voltage level and a ground level.
Subsequently, a restore operation is carried out. In this period, the amplified signal of the bit line /BL is rewritten in a cell.
When the restore operation is completed, the bit lines BL and /BL are restored to a pre-charge state.
Regarding the operation voltage of the semiconductor memory device operated in the aforementioned manner, as described above, the operation voltage margin for the threshold voltages of the NMOS transistor and the PMOS transistor included in the sense amplifier becomes insufficient. As a result, the operation feature of the sense amplified deteriorates.
In particular, the difference of the threshold voltage between both sides of PMOS transistors of the sense amplifier is much greater than that of NMOS transistors of the sense amplifier. Therefore, in the case of a low voltage operation, amplification driving capability of the sense amplifier decreases.
In order to solve these problems, the conventional semiconductor memory device employs an over-drive method so as to improve PMOS driving capability.
However, since a PMOS offset feature has a significant effect on the over-drive method, erroneous data may be output from the sense amplifier.